Tag Archives: Carbon nanotubes

What next for integrated circuits?

There is currently a big problem in the semiconductor industry. While technological progress and commercial pressure demand that electronics must be made smaller and faster, we are getting increasingly close to the fundamental limits of what can be achieved with current materials.

In the last couple of weeks, two academic papers have come out which describe ways in which we might be able to get around these limitations.

Size matters

A quick reminder about how transistors work. (You can read more detail here.) Transistors are switches which can be either on or off. They have a short conducting channel through which electricity can flow. When they are on, electrical current is flowing through them, and when they are off it is not. They have three connections, one which supplies current (called the source), one which collects it (the drain), and one which controls whether the channel is open or closed.

A rough sketch of a transistor, showing the contact length LC and the gate length LG.

There is something called the International Technology Roadmap for Semiconductors which lays out targets for improvements in transistor technology which companies such as Intel are supposed to aim for. The stages in this plan are called “nodes”, which are described by the size of the transistor. Having smaller transistors is better because you can fit more into a chip and do more computations in a given space.

At the moment, transistors at the 14 nanometre node are being produced. This means that the length of the gate/channel is 14nm (a nanometre is one millionth of a millimetre). According to the roadmap, within a decade or so, the channel length is supposed to be as short as 3nm. But, overall, transistors are rather bigger than this length, in part because of the size of the source and drain contacts. Transistors at the 3nm node will have an overall size of about 40nm.

Carbon nanotube transistors

The first paper I want to mention, which came out in the journal Science, reports the fabrication of a transistor made out of different materials which allows the overall size to be reduced. Instead of using doped silicon for the contacts and channel,  these researchers made the channel out of a carbon nanotube, and contacts from a cobalt-molybdenum alloy.

Carbon nanotubes are pretty much graphene which has been rolled up into a cylinder which is a few nanometres wide. Depending on the details, they can have semiconducting electronic properties which are excellent for making transistors from, but they also are interesting for a whole range of other reasons.

By doing this, they could make a channel/gate region of about 11 nm long, with two contacts that were about 10nm each. Even with some small spacers, the total width of the transistor was only 40nm. This should satisfy the demands of the 3nm node of the roadmap, even though the channel is nearly four times as long as that.

3D chips

The second approach is completely different. At the moment, integrated circuits are mostly made in a single layer, although there are some exceptions to this in the most modern chips. This means that the various parts of the chip that do calculations and store memory can be located quite a long way away from each other. This can lead to a bottleneck as data is moved around to where it is needed.

A group of researchers, publishing in the journal Nature, designed an entirely new architecture for a chip in which the memory, computation, input, and output were all stacked on top of each other. This means that even though the transistors in their device are not particularly small, the data transfer between memory and computation can all happen at the same time. This leads to a huge increase in speed because the bottleneck is now much wider.



The prototype they designed was actually a gas sensor, and a rough idea of its construction is shown in the sketch above. Gas molecules fall on the top layer, which is made up of a large number of individual detectors that can react to single molecules. These sensors can then write the information about their state into the memory which is directly below it via vertical connections that are built into the chip itself.

The point of the sensor is to work out what type of gas has fallen on it. To do this, the information stored in the memory from the sensors must be processed by a pattern recognition algorithm which involves a lot of calculations. This is done by a layer of transistors which are placed below the memory, and are directly connected to it. In the new architecture, the transistors doing the computation have much quicker access to the data they are processing than if it were stored in another location on the chip. Finally, an interface layer allows the chip to be controlled and through which it outputs the result of the calculation are below the transistors, again connected vertically.

The paper shows results for accurate sensing of gaseous nitrogen, lemon juice, rubbing alcohol, and even beer! But that’s not really the crucial point. The big new step is the vertical integration of several components which would otherwise be spaced out on a chip. This allows for much quicker data processing, because the bottleneck of transferring data in and out of memory is drastically reduced.

So, the bottom line here is that simply finding ways to make traditional silicon transistors smaller and smaller is only one way to approach the impending problems facing the electronics industry. It will be a while before innovations like this become the norm for consumer electronics, and perhaps these specific breakthroughs will not be the eventual solution. But, in general, finding new materials to make transistors from and designing clever new architectures are very promising routes forward.